It is often necessary to synchronize data across different clock domains. As clock frequencies increase, however, it has become more difficult to achieve the proper timing required for such synchronization.
FIG. 1 shows a typical situation that requires synchronization of an asynchronous data signal. In this example, a memory controller 10 generates a clock signal 12 that is in turn provided to a memory device 14 to coordinate data transfers. In response to clock signal 12, memory device 14 generates a data signal 16 that is in turn received by the memory controller 10. Although the data signal is generated synchronously with clock signal 12, propagation delays between the memory device 14 and memory controller 10 cause the data signal to lose synchronization by the time it reaches controller 10. Furthermore, propagation delays are different for the different memory devices of the system, so that received data signals will have different phases depending on their sources. This brings about the need for synchronization within controller 10.
FIG. 2 shows a typical prior art circuit for synchronizing a received data signal DATAIN for use with an internal clock signal CLK2. In this example, a clock source 20 generates multiple reference clock signals having known, calibrated phase relationships between each other. For example, clock source 20 might generate eight clock signals having phases that vary by 45° from each other. Clock generation circuits 22 and 23 receive the reference clock signals produce respective clock signals CLK1 and CLK2 having phases that are specified by supplied digital phase control values PHASE1 and PHASE2.
In this example, CLK2 is the internal clock signal to which received data signals will be synchronized. CLK2 is received by the clock input of a latch or flip/flop 24 to latch the received data signal. Prior to this, however, the data signal is sampled and then synchronized by latches or flip/flops 25 and 26.
During normal operation, latch 25 is clocked by clock signal CLK1. This causes latch 25 to sample the received data signal DATAIN and to produce a captured data signal CDATA. The appropriate phase for CLK1 and the requisite digital value of PHASE1 to produce this phase are determined during an initialization procedure. During the initialization procedure, repeated attempts are made to read received data using different PHASE1 values and corresponding CLK1 phases. As a result of these attempts, a range of PHASE1 values is recorded as yielding valid results, and an intermediate one of these values is chosen for future use. During subsequent read operations, PHASE1 is set to this chosen value. Note that this setting might vary during operation, as data is received from different devices with different propagation delays.
As a result of the initialization procedure, CLK1 has an undetermined phase relationship with CLK2. Because of this, the captured data signal CDATA cannot be guaranteed to meet setup and hold times of any downstream latches or other sampling devices that are clocked by CLK2.
To ensure adequate setup and hold times at the input of latch 26, latches 26a and 26b are configured to clock CDATA either in phase with CLK2 or at 180° relative to CLK2, depending on the phase relationship of CLK2 to CLK1. Specifically, each of latches 26a and 26b receives CDATA as a data input. Latch 26a is clocked by CLK2 and Latch 26b is clocked by CLK2* (the “*” symbol is used to indicate negation or inversion). The outputs of the latches 26a and 26b are connected to the inputs of a two-to-one multiplexer 27. Depending on the value of its select input, the multiplexer presents either the clocked signal from 26a or the clocked signal from latch 26b. 
The select input of multiplexer 27 receives a detect signal 30 from a phase detection circuit 31. Phase detection circuit 31 compares CLK1 and CLK2 to determine whether the phase of CLK2 relative to CLK1 is greater than 90°. If the phase is greater than 90°, detect signal 30 is asserted high to select the latched signal from latch 26a, which has been latched on the rising edge of CLK2. If the phase is less than 90°, detect signal 30 is asserted low to select the latched signal from latch 26b, which as been latched on the falling edge of CLK2.
Phase detection circuit 31 is implemented with a latch or flip/flop 32 and a signal delay element 33. Latch 32 has a clock input that receives CLK2. CLK1 is delayed 90° by delay element 33 and then provided to the data input of latch 32. This produces an output from latch 32 that is positive only if CLK2 lags CLK1 by more than 90°.
The described circuit is adequate, and has been used with success in various designs. At higher clock frequencies, however, the design effort becomes significant. Furthermore, typical delay elements (such as delay element 33) and other types of phase shifting circuits impose significant area and power requirements. Also, the phase at which the phase detection circuit triggers is fixed in the circuit described above. Therefore, it would be desirable to eliminate the need to compare clock signals to derive phase information and phase comparisons.